This invention relates to a numerical control system and in particular a numerical control system for lathes which executes a feed per minute instruction mode, feed per revolution instruction mode and a thread cutting feed instruction mode.
Circuits known as digital differential analyzers (DDA) or pulse multipliers are used, in plural numbers, for arithmetic calculation circuits in a numerical control system (hereinafter referred to as an NC system) for lathes. The DDA is adapted to deliver a relatively equidistant pulse train signal of, for example, f.sub.0 = (M/2.sup.24).times.f.sub.1 when it receives a pulse train signal with a frequency f.sub.1 at its pulse input terminal and a data amount M at its data input terminal (2.sup.24 is a value when a register of the DDA constitutes a binary 24-bit configuration). In presently available NC systems require a feed speed of 10,000,000 (pulse/min) and a minimum pulse division capability of 1 (.mu.m/pulse) is required as a minimum input pulse unit to a servo system. In order to meet with these requirements the DDA must deliver an output pulse having a pulse frequency f.sub.0 with a maximum value of 10,000,000 (pulse/min) = 166,666 (pulse/sec). This means that an output pulse must be delivered at a speed of (1/166,666) = 6 (.mu.s).
It is, however, impossible for the NC system, after the NC system receives an instruction, to execute the instruction in a time of 6 .mu.s, since the required time is very small. Even when the DDA effects a calculation using a high speed computer, at least more than 20 steps are required for effecting one DDA calculation. Since a time of 6 (.mu.s)/20 (steps) = 0.3 (.mu.s/step) is allotted to one step instruction, an arithmetic calculation of the DDA can not be made using the high speed computer. Furthermore, a clock oscillator must deliver a very high frequency of 2.sup.48 (pulse/min) .apprxeq. 10.sup.12 (pulse/sec) i.e., more than 10.sup.6 (MHz). As an arithmetic logic circuit requires such a rapid clock pulse rate from the logical standpoint, it is not possible to realize such a circuit arrangement using now available logic circuits.
In a thread cutting mode, with f.sub.0 (pulse/rev) representing a pulse rate from a spindle pulse generator, the DDA can not deliver a pulse with a pulse rate of f.sub.0 (pulse/rev). In consequence, the conventional NC system can not cut a thread with a pitch of more than f.sub.0 (.mu.m/rev). When a thread with a larger pitch is to be cut, it is necessary to increase a pulse generating rate from the spindle pulse generator. The pulse generator with such a high pulse dividing capability is high in cost and, when the spindle is rotated at high speed, problem is presented, due to a high output frequency of the pulse generator, with respect to a connection to the pulse generator frequency characteristics and so on. This presents problems from a practical viewpoint.